1. Field of the Invention
The present invention relates to displays, and in particular to high definition plasma displays with many scanning lines, and in particular to modifying voltage waveforms applied to electrodes during an address period to prevent addressing failure.
2. Description of the Related Art
Plasma display panels (PDPs) offer a large screen to display an image thereon. In high definition (HD-PDPs), there is a large number of scanning lines in the display. However, a problem exists in that address discharge is more apt to fail in the addressing of the later lines of pixel selection. What is needed is a way to overcome the problem of increased risk of failure in addressing the higher number scan lines in a display with many scanning lines without lengthening the temporal size of the address period.